(1) Field of the Invention
The present invention relates to the field of computer multiprocessor system architecture, particularly the field of memory systems having error correction code protected memory.
(2) Prior Art
In the design of a multiprocessor system architecture, a memory system is connected to a system bus for storing data generated and used by a plurality of input/output devices similarly connected to the bus. A central processing unit (CPU) controls the flow of data on the bus by reading the data generated by an input device and writing the data to either an output device or to memory. Data is stored in a memory array through the use of a memory system in which a memory controller controls the flow of data on a data path connected between the system bus and a memory array. When the CPU initiates a write cycle to write data to the memory array, it generates address and control signals, hereinafter referred to as instructions, and a plurality of byte enable signals which are transmitted to the memory controller to designate specific data strings and the specific locations where those data strings are to be stored. In response, the memory controller of a prior art memory system transmits the byte enable signals to the data path via a byte enable bus having a corresponding number of byte enable lines so as to permit the passage of selected data strings placed on the data path to the memory array.
In computers using error correction code (ECC) protected memory arrays, data strings stored in the memory array, hereinafter called memory strings, are protected by ECC codes so as to maintain data consistency and prevent erroneous overwriting of data. The ECC codes are generated by a coding means in the data path and are connected to the data strings while the data strings are temporarily stored in a data path buffer. The data strings and their associated codes are subsequently transferred to the memory array for storage as memory strings and associated codes. During a normal full word write operation, the CPU instructs the memory controller to write into memory the entire data string placed in the data path buffer. When a full word write occurs, the memory controller instructs the coding means to generate an ECC code for the data string currently stored in the data path buffer and sends high (or active) all byte enable lines corresponding to each byte of the data string in order to designate that the entire data string is to be written into the memory array along with the ECC code.
In order to update the memory strings stored in the memory array with new data, the CPU generates a partial word write operation which triggers a read-modify-write operation. The memory controller instructs the data path to read a specific memory word from the memory array and store it in the data path buffer. Next, the memory controller instructs the data path to read a selected data string from the system bus and to save the data string in the data path buffer. The data bytes of the memory string to be saved are merged with new data bytes of the data string by overwriting only those data bytes of the memory string which correspond to low (or inactive) byte enable signals. A new ECC code is generated for the modified memory string and the combination is then written back into the memory array.
In prior art memory systems using ECC protected memory, the memory controller and data path buffer each comprise a plurality of byte enable pins for transmitting a corresponding number of byte enable signals along a byte enable bus. As mentioned above, the purpose of the plurality of byte enable signals is to designate which bytes of the memory string, corresponding to specific byte enable signals, are to be protected during the overwrite with the new data bytes to obtain the modified word in a partial word write operation. The problem with the above method is that in order to support a partial word write operation to an ECC protected memory array, the total number of input/output pins required to convey the byte enable information between the memory controller and the data path buffer corresponds to twice the number of data bytes in a memory string. In most prior art memory systems, the memory strings comprise eight data bytes so that eight pins are required for each of the memory controller and the data path buffer. This is a problem with most memory system designs which are pin bound since it is obviously desirable to minimize the number of pins needed to support the seldom utilized partial word write operation. With the number of input/output pins minimized, the multiprocessor system architecture may then be incorporated into smaller and cheaper integrated circuit packages. Furthermore, through the use of a multiplexed byte enable bus, other memory system operations may be facilitated due to the fact that the same multiplexed bus can be used to transmit other information and signals between the memory controller and the data path buffer.
It is therefore an object of the present invention to provide a method and an apparatus for minimizing the number of pins required in a memory system for support of partial word write operations to an ECC protected memory array with no resulting performance penalty.
It is a further object of the present invention to provide a design for a memory system using eight byte memory strings and requiring four clocks per memory read in which only two byte enable signals are required to support partial word write operations.
Yet another object of the invention is to provide a method and apparatus for a multiplexed byte enable bus in which the maximum efficient use of the memory controller and data path of a memory system can be achieved.